DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era
IEEE Design & Test
A design approach for radiation-hard digital electronics
Proceedings of the 43rd annual Design Automation Conference
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As process technologies continue to scale into the nanometer regime, devices are becoming significantly more unreliable. Many forms of unreliability manifest as transient faults and can cause intermittent random logic upsets. These logic upsets are often caused by natural radiation (neutrons and alpha particles) or on-chip noise (cross-coupling, supply drop, or flicker noise). This research improves reliability by using non-uniform redundancy. Specifically, we present a dynamic programming algorithm that considers many possible topological redundancies, yet maintains a linear run-time due to efficient pruning of suboptimal solutions. Our algorithm provides designers with a Pareto-optimal set of solutions that trade reliability for area. Compared to existing Triple Modular Redundancy (TMR), we see similar reliability with only 35% area overhead instead of 326%.