DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous area and delay minimum K-LUT mapping for K-exact networks
Integration, the VLSI Journal
FPGA Technology Mapping Using Logic Blocks with Independent LUTs
FPGA Technology Mapping Using Logic Blocks with Independent LUTs
Notes on “Complexity of the lookup-table minimization problem for FPGA technology mapping”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
General technology mapping for field-programmable gate arrays based on lookup tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A technology mapping algorithm for heterogeneous FPGAs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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The logic blocks (CLBs) of a lookup table (LUT) based FPGA consist of one or more LUTs, possibly of different sizes. In this paper, we focus on technology mapping for CLBs with several independent LUTs of two different sizes (called ICLBs). The Actel ES6500 family is an example of a class of commercially available ICLBs. Given a tree network with n nodes, the only previously known approach for minimum area tree-based mapping to ICLBs was a heuristic with running time &THgr;(nd+1, where d is the maximum indegree of any node. We give an O(n3) time exact algorithm for mapping a given tree network, an improvement over this heuristic in terms of run time and the solution quality. For general networks, an effective strategy is to break it into trees and combine them. We also give an O(n3) exact algorithm for combining the optimal solutions to these trees, under the condition that LUTs do not go across trees. The method can be extended to solve mapping onto CLBs that can be configured into different ICLBs, (e.g. Xilinx' XC4000E).