DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A global approach to circuit size reduction
Proceedings of the fifth MIT conference on Advanced research in VLSI
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Efficient tree pattern matching (extended abstract): an aid to code generation
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Optimal Code Generation for Expression Trees
Journal of the ACM (JACM)
Efficient string matching: an aid to bibliographic search
Communications of the ACM
An Artificial Intelligence Approach to VLSI Design
An Artificial Intelligence Approach to VLSI Design
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
The MIMOLA design system a computer aided digital processor design method
DAC '79 Proceedings of the 16th Design Automation Conference
LSS: a system for production logic synthesis
IBM Journal of Research and Development
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Instruction set mapping for performance optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs
SAC '98 Proceedings of the 1998 ACM symposium on Applied Computing
Behavioral synthesis with systemC
Proceedings of the conference on Design, automation and test in Europe
AGENDA: an attribute grammar driven enviornment for the design automation of digital systems
Proceedings of the conference on Design, automation and test in Europe
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Programming-language compilers generate code targeted to machines with fixed architectures, either parallel or serial. Compiler techniques can also be used to generate the hardware on which these programming languages are executed. In this paper we demonstrate that many compilation techniques developed for programming languages are applicable to compilation of register-transfer hardware designs. Our approach uses a typical syntax-directed translation → global optimization → local optimization → code generation → peephole optimization method. In this paper we will describe ways in which we have both followed and diverged from traditional compiler approaches to these problems and compare our approach to other compiler oriented approaches to hardware compilation.