Automated logic synthesis of random pattern testable circuits

  • Authors:

  • Nur A. Touba;Edward J. McCluskey

  • Affiliations:

  • Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, California;Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, California

  • Venue:
  • ITC'94 Proceedings of the 1994 international conference on Test
  • Year:
  • 1994

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Abstract

Previous approaches to designing random pattem testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken in this paper is to consider random pattern testability during logic synthesis. An automated logic synthesis procedure is presented which takes as an input a two-level representation of a circuit and a constraint on the minimum fault detection probability (threshold below which faults are considered r.p.r.) and generates a multilevel implementation that satisfies the constraint while minimizing the literal count. The procedure identifies r.p.r. faults and attempts to "eliminate" them through algebraic factoring. If that is not possible, then test points are inserted during the synthesis process in a way that minimizes the number of test points that are required. Results are shown for benchmark circuits which indicate that the proposed procedure can generally reduce the random pattern test length by at least an order of magnitude with only a small area overhead.