Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
IEEE Transactions on Computers
Synthesis of Native Mode Self-Test Programs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Behavioral synthesis for testability
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test Point Insertion for Compact Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Automated logic synthesis of random pattern testable circuits
ITC'94 Proceedings of the 1994 international conference on Test
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The test point insertion problem is that of selecting t nodes in a combinational network as candidates for inserting observable test points, so as to minimize the number of test vectors needed to detect all single stuck-at faults in the network. In this paper we describe a dynamic programming approach to selecting the test points and provide an algorithm that inserts the test points optimally for fanout-free networks. We further extend this algorithm to general combinational networks with reconvergent fanout. We also analyze the time complexity of the algorithm and show that it runs in &Ogr;(n-t) time, where n is the size of the network and t is the number of test points to be inserted.As a side result we show that we can compute minimal test sets for a restricted class of networks that includes fanout. This extends previous results which were limited to fanout-free networks.