A dynamic programming approach to the test point insertion problem
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A hybrid algorithm for test point selection for scan-based BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Accelerated Compact Test Set Generation for Three-State Circuits
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Point Insertion for an Area Efficient BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Accelerated Test Points Selection Method for Scan-Based BIST
ATS '97 Proceedings of the 6th Asian Test Symposium
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Low Overhead Test Point Insertion For Scan-Based BIST
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Point Placement to Simplify Fault Detection
IEEE Transactions on Computers
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Impact of Test Point Insertion on Silicon Area and Timing during Layout
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation
Journal of Electronic Testing: Theory and Applications
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Compacting test vector sets via strategic use of implications
Proceedings of the 2009 International Conference on Computer-Aided Design
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Efficient production testing is frequently hampered because(cores in) current complex digital circuit designs requiretoo large test sets, even with powerful ATPG tools thatgenerate compact test sets. Built-In Self-Test approachesoften suffer from fault coverage problems, due torandom-resistant faults, which can successfully be improved bymeans of Test Point Insertion (TPI). In this paper, we evaluatethe effect of TPI for BIST on the compactness of ATPGgenerated test sets and it turns out that most often a significanttest set size reduction can be obtained. We alsopropose a novel TPI method, specifically aiming at facilitatingcompact test generation, based on the 'test counting'technique. Experimental results indicate that the proposedmethod results in even larger, and moreover, more consistentreduction of test set sizes.