Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Test Point Insertion for Compact Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
The Testability Features of the 3rd Generation Coldfire® Family of Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
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The industry is scrambling to prevent a potentialexplosion in nanometer technology test costwhere the cost to test a device is closing in onthe cost to manufacture it. Across the testindustry, entire methodologies are being re-addressed,tester costs are being scrutinized, andtest vector count is being reduced. In this paper,a new concept is presented that allows forlowering the cost of test by utilizing the testerresources more efficiently. The solutionpresented brings together an existing concept ofbeing able to reconfigure scan chains withmethods that allow the same test pattern data tobe applicable for all configurations. A data-modelis created to emphasize the use of suchtechnology. The concepts developed in this paperare compatible with other test cost reductionmethods.