Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Point Insertion for Compact Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Proceedings of the conference on Design, automation and test in Europe
An Evaluation of Pseudo Random Testing for Detecting Real Defects
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing
IEEE Design & Test
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
On the Size and Generation of Minimal N-Detection Tests
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
On N-Detect Pattern Set Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
Zchaff2004: an efficient SAT solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Improving the testability and reliability of sequential circuits with invariant logic
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which in turn makes simple approaches for testing inadequate. Using n-detect testing can improve detect coverage; however, this approach can greatly increase the test set size. In this proof-of-concept paper we investigate the use of logic implication checkers, inserted in hardware, as an aid in compacting n-detect test sets. We show that checker hardware with minimal area overhead can reduce test set size by up to 25%. In addition, this implication checker can serve a dual purpose for online error detection.