DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Algorithms for finding patterns in strings
Handbook of theoretical computer science (vol. A)
Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Robust IP watermarking methodologies for physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Robust techniques for watermarking sequential circuit designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Journal of the ACM (JACM)
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Digital Image Watermarking: An Overview
ICMCS '99 Proceedings of the IEEE International Conference on Multimedia Computing and Systems - Volume 2
Watermarking integer linear programming solutions
Proceedings of the 39th annual Design Automation Conference
A watermarking system for IP protection by a post layout incremental router
Proceedings of the 42nd annual Design Automation Conference
Behavioral synthesis techniques for intellectual property protection
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Efficient and Reliable Watermarking System for IP Protection
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking that guarantees preservation of timing constraints by judiciously selecting parts of the design specification on which watermarking constraints can be imposed. The technique is applied during the mapping of logical elements to instances of realization elements in a physical library. The generic technique is applied to two steps in the design process: combinational logic mapping in logic synthesis and template matching in behavioral synthesis. The technique is fully transparent to the synthesis process, and can be used in conjunction with arbitrary synthesis tools. Several optimization problems associated with the application of the technique have been solved. The effectiveness of the technique is demonstrated on a number of designs at both logic synthesis and behavioral synthesis.