Watermarking techniques for intellectual property protection
DAC '98 Proceedings of the 35th annual Design Automation Conference
Robust IP watermarking methodologies for physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Intellectual property protection by watermarking combinational logic synthesis solutions
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Watermarking while preserving the critical path
Proceedings of the 37th Annual Design Automation Conference
Watermarking graph partitioning solutions
Proceedings of the 38th annual Design Automation Conference
Watermark Design Pattern for Intellectual Property Protection in Electronic Commerce Applications
HICSS '00 Proceedings of the 33rd Hawaii International Conference on System Sciences-Volume 6 - Volume 6
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fingerprinting techniques for field-programmable gate array intellectual property protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Watermarking System for IP Protection by Buffer Insertion Technique
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An Efficient and Reliable Watermarking System for IP Protection
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
| Hi-index | 0.00 |
In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then embedded by using an incremental router into the layout design. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated. The incremental router consists of a rip-up and a special re-router that inserts redundant bends into wires probabilistic. We evaluated the technique on various generated benchmark circuits to validate the completeness of the procedure. The results show it achieves almost 100% success for embedding with no extra area cost on design performances.