A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits

  • Authors:
  • P. Beerel;W. Chou;K. Yun

  • Affiliations:
  • EEB 350, MC 2562, EE-Systems Dept., USC, Los Angeles, CA;EEB 350, MC 2562, EE-Systems Dept., USC, Los Angeles, CA;EBU1-4402, MC 0407, Dept. of ECE, UCSD, La Jolla, CA

  • Venue:
  • EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
  • Year:
  • 1996

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Abstract