Automatic technology mapping for generalized fundamental-mode asynchronous designs
DAC '93 Proceedings of the 30th international Design Automation Conference
Representing and modeling digital circuits
Representing and modeling digital circuits
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Automatic technology mapping for asynchronous designs
Automatic technology mapping for asynchronous designs
Unifying synchronous/asynchronous state machine synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Automatic Verification of Timed Circuits
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Automatic synthesis of gate-level timed circuits with choice
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Synthesis of hazard-free asynchronous circuits with bounded wire delays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Hi-index | 0.00 |
This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the design process to optimize the implementation. Our procedure begins with a timed specification and a delay-annotated gate library description which must include 2-input AND gates, OR gates, and C-elements, but optionally can include higher-fanin gates, AND-OR-INVERT blocks, and generalized C-elements. Our procedure first generates a technology-independent timed circuit netlist composed of possibly high-fanin AND gates, OR gates, and 2-input C-elements. The procedure then investigates simultaneous decompositions of all high-fanin gates by adding state variables to the the specification and performing resynthesis. Although multiple decompositions are explored timing information is utilized to significantly reduce their number. Once all gates are sufficiently decomposed, the netlist can be mapped to the given gate library, taking advantage of any compact complex gates available. The decomposition and resynthesis steps have been fully automated within the synthesis tool ATACS and we present results for several examples.