Modeling and synthesis of timed asynchronous circuits
EURO-DAC '94 Proceedings of the conference on European design automation
Lazy transition systems: application to timing optimization of asynchronous circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Conformance and mirroring for timed asychronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timed Verification of Asynchronous Circuits
Concurrency and Hardware Design, Advances in Petri Nets
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
Technology mapping of timed circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Verification of Delayed-Reset Domino Circuits Using ATACS
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automatic synthesis of gate-level timed circuits with choice
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Verification system for real-time specification based on extended real-time logic
RTCSA '95 Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications
State space computation and analysis of Time Petri Nets
Theory and Practice of Logic Programming
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Testing real-time systems using UPPAAL
Formal methods and testing
Testing real-time systems under uncertainty
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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