Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Journal of the ACM (JACM)
Representing and modeling digital circuits
Representing and modeling digital circuits
Symbolic approximations for verifying real-time systems
Symbolic approximations for verifying real-time systems
Real-Time Systems, Abstractions, Languages, Design Methodologies, and Tools
Real-Time Systems, Abstractions, Languages, Design Methodologies, and Tools
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Quantitative Temporal Reasoning
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Automatic Verification of Timed Circuits
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Logics and Models of Real Time: A Survey
Proceedings of the Real-Time: Theory in Practice, REX Workshop
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A real-time system consists of many concurrent processes and behaves on strict timing conditions. It is important to verify the timing conditions of a real-time system. In this paper, we propose extended TCTL (Timed CTL) and effective real-time model checking as follows. (1) The timing description of extended TCTL consists of both freeze quantification and bounded temporal operator. For this extension, extended TCTL admits timing constraints between distant contexts. (2) Real time model checking consists of both labelling algorithm and geometric region method. For this method we can avoid the state explosion problem. We have develop the verification system, and show our method to be effective.