An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
Designing Circuits with Partial Scan
IEEE Design & Test
Produktionstest synchroner Schaltwerke auf der Basis von Pipelinestrukturen
GI - 18. Jahrestagung II, Vernetzte and komplexe Informatik-Systems
Cellular scan test generation for sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
Partial scan selection for user-specified fault coverage
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path, existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan.Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes.Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible.