Identification of unsettable flip-flops for partial scan and faster ATPG
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
High-level variable selection for partial-scan implementation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications
Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
Behavioral-Level DFT via Formal Operator Testability Measures
Journal of Electronic Testing: Theory and Applications
Impact of Partial Reset on Fault Independent Testing and BIST
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Partial Scan Using Multi-Hop State Reachability Analysis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Using a software testing technique to identify registers for partial scan implementation
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
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