Identification of unsettable flip-flops for partial scan and faster ATPG

Authors:
Ismed Hartanto;Vamsi Boppana;W. Kent Fuchs
Affiliations:
Design Technology Center, Hewlett-Packard Co., Palo Alto, CA and Coordinated Science Laboratory, University of Illinois, Urbana, IL;Coordinated Science Laboratory, University of Illinois, Urbana, IL;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Venue:
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Year:
1997

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Abstract

State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (hip-hops) that are either difficult to set or unsettable. This is achieved by performing test generation on certain transformed circuits to identify state elements that are not settable to specific logic values. Two applications that benefit from this identification are sequential circuit test generation and partial scan design. The knowledge of the state space is shown to be useful in creating early backtracks in deterministic test generation. Partial scan selection is also shown to benefit from the knowledge of the difficult-to-set hip-hops. Experiments on the ISCAS89 circuits are presented to show the reduction in time for test generation and the improvements in the testability of the resulting partial scan circuits.