A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
Logic BIST Using Constrained Scan Cells
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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This paper proposes a method to select observation points and flip-flops for partial reset. The method does not target minimum DFT insertion but a maximum improvement on testability. The proposed non-scan approach allows a at-speed testing. Experimental results show that the method achieves 100% fault coverage and 100% fault efficiency for benchmark circuits while requiring less ATPG effort (CPU time) with no scan necessity.