Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage
ATS '00 Proceedings of the 9th Asian Test Symposium
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Transformed pseudo-random patterns for BIST
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A novel pattern generator for near-perfect fault-coverage
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
Built-in generation of multicycle functional broadside tests with observation points
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a novel scan cell based control pointinsertion technique which eliminates timing degradation ofconventional control points in built-in self test (BIST) applications.In this approach, control points are encoded intoscan chains. Observation points are applied to enhancefault coverage. At each phase, a set of control points are activatedto detect a set of target faults. Compared to conventionaltest point insertion, scan cell based control points improvecontrollability of the core logic without compromisingtiming performance of circuit under test (CUT). Experimentalresults show that close to stuck-at fault coverage by automatictest pattern generation (ATPG) can be achieved byour BIST method.