The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
Designing Circuits with Partial Scan
IEEE Design & Test
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
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We present a partial scan approach, which aims at reducing both area overhead and performance degradation caused by test logic. Given a target speed and an initial design that meets the target, the algorithm selects a minimum set of scan flip-flops, if they exist, that (1) will break all sequential cycles and (2) will not violate the performance requirement after the scan logic is added. If such a set does not exist, the algorithm will find a set of scan flip-flops in which (1) all sequential cycles are broken and (2) the total area increase caused by the scan logic and the subsequent performance optimization to meet the target speed is minimized.Experimental results on some of the ISCAS'89 sequential circuits are presented as well as comparisons between the new method and the existing methods. For circuits synthesized by automatic synthesis tools, we suggest a new design flow, which selects/inserts the partial scan logic after area optimization, but before performance optimization. For meeting both performance and testability requirements, the new design flow tends to produce designs with less area increase than the traditional design flow, which considers testability and adds test logic after performance optimization.This work represents an important concept for considering the three major design parameters, namely, performance, area, and testability, together during the synthesis phase for obtaining the right partial scan solution.