The CMU design automation system: An example of automated data path design
DAC '79 Proceedings of the 16th Design Automation Conference
Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
Facet: A procedure for the automated synthesis of digital systems
25 years of DAC Papers on Twenty-five years of electronic design automation
A generalized interconnect model for data path synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An automated data path synthesizer for a canonic structure, implementable in VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
High-level synthesis for easy testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Experiments with the SLIM Circuit Compactor
DAC '83 Proceedings of the 20th Design Automation Conference
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Automated Synthesis of Digital Hardware
IEEE Transactions on Computers
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A bus oriented interconnection of registers and data operators is the dominant mode of design for the data paths of digital systems. A study of ten processor implementations, ranging in size from microprocessors to large mainframes, spanning almost 20 years in the practice of digital design, indicated a strong similarity. From this study bus style primitives and generic bus models were developed. The generic bus models were simplified to match each of the ten processors composing the study. An algorithm for generating a bus style design is presented. The algorithm is used to generate the data paths of the PDP-11/40 resulting in lower cost and shorter delays than the original implementation. Finally, the paper concludes with a discussion of the bus synthesis algorithm's implementation and its role in the CMU functional-to-hardware Design Automation System.