Optimal selection of functional components for microprogrammable central processing units
MICRO 5 Conference record of the 5th annual workshop on Microprogramming
On proving the correctness of optimizing transformations in a digital design automation system
DAC '81 Proceedings of the 18th Design Automation Conference
The modeling and synthesis of bus systems
DAC '81 Proceedings of the 18th Design Automation Conference
A technology relative Logic Synthesis and Module Selection system
DAC '81 Proceedings of the 18th Design Automation Conference
Algorithms for multiple-criterion design of microprogrammed control hardware
DAC '81 Proceedings of the 18th Design Automation Conference
A formal method for the specification, analysis, and design of register-transfer level digital logic
DAC '81 Proceedings of the 18th Design Automation Conference
Register-transfer level digital design automation: The allocation process
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Measuring designer performance to verify design automation systems
DAC '77 Proceedings of the 14th Design Automation Conference
The MIMOLA design system a computer aided digital processor design method
DAC '79 Proceedings of the 16th Design Automation Conference
The MIMOLA design system: Detailed description of the software system
DAC '79 Proceedings of the 16th Design Automation Conference
Automatically decomposing signal processing applications on multiprocessors.
Automatically decomposing signal processing applications on multiprocessors.
Methods Used in an Automatic Logic Design Generator (ALERT)
IEEE Transactions on Computers
An architectural research facility: ISP descriptions, simulation, data collection
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
The CMU RT-CAD system: an innovative approach to computer aided design
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
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This paper describes a portion of the Carnegie-Mellon University Design Automation (CMU-DA) research. This part involves the design and construction of a data-memory allocator, consisting of a set of algorithms and data structures which synthesize hardware at the register-transfer level from a behavioral description written in ISP. The allocator selects registers and data operators and interconnects them with data paths to form a data part capable of implementing the data operations specified in the behavior. Results indicate that the allocator's performance compares favorably with a human designer when designing an elevator controller and a reduced PDP-8/E. Although optimal designs cannot be guaranteed, upper bounds for the number of components used can be derived from the ISP description.