Methods Used in an Automatic Logic Design Generator (ALERT)

  • Authors:
  • T. D. Friedman; Sih-Chin Yang

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1969

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Abstract

The ALERT system converts preliminary high-level descriptions of computers into logic. The input to ALERT depicts the architecture of a proposed machine in a form of Iverson notation. As output, the architecture is "compiled" into Boolean equations, which may then be converted into standard computer circuits.