The Organization of Microprogram Stores
ACM Computing Surveys (CSUR)
Register-transfer level digital design automation: The allocation process
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
Automatic synthesis of microcontrollers
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Optimization of the influence of problem modifications on given microprogrammed controllers
DAC '80 Proceedings of the 17th Design Automation Conference
The MIMOLA design system a computer aided digital processor design method
DAC '79 Proceedings of the 16th Design Automation Conference
Automatically decomposing signal processing applications on multiprocessors.
Automatically decomposing signal processing applications on multiprocessors.
Formal semantics for the automated derivation of micro-code
DAC '82 Proceedings of the 19th Design Automation Conference
Automated Synthesis of Digital Hardware
IEEE Transactions on Computers
An Abstract Model of Behavior for Hardware Descriptions
IEEE Transactions on Computers
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This paper describes two algorithms designed to optimize memory size and controller performance for a microprogrammed controller. The algorithms accept two inputs: a set of interconnected registers and logical operators called the data paths, and a control flow graph which describes how these data paths are to be exercised. The Autonomy algorithm identifies data path elements which should be controlled directly from the microword without encoding. This algorithm aids the effectiveness of the subsequent encoding algorithm by eliminating some signals from consideration. A second algorithm, the Attraction algorithm, determines which microoperations will execute in parallel and which will be encoded into separate microinstruction formats. This algorithm accepts a microword width constraint and implements parallel operations in the microcode and the corresponding encoding. Both the parallelism and the encoding are determined by the algorithm. Application of these algorithms to an example, the PDP**-11/40, has produced a control store design 14 percent wider and equal in parallelism to an equivalent portion of the human design.