A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Digital signal processing: theory, applications, and hardware
Digital signal processing: theory, applications, and hardware
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Reconfigurable scan chains: a novel approach to reduce test application time
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for testability
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A comparative study of design for testability methods using high-level and gate-level descriptions
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
A Built-In Self-Testing Approach for Minimizing Hardware Overhead
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
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ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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DAC '96 Proceedings of the 33rd annual Design Automation Conference
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Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
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IEEE Design & Test
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EDTC '97 Proceedings of the 1997 European conference on Design and Test
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ITC '97 Proceedings of the 1997 IEEE International Test Conference
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ISSS '96 Proceedings of the 9th international symposium on System synthesis
A DFT method for time expansion model at register transfer level
Proceedings of the 44th annual Design Automation Conference
High-level test synthesis with hierarchical test generation for delay-fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
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This paper presents a non-scan design-for-testability technique applicable to register-transfer (RT) level data path circuits, which are usually very hard-to-test due to the presence of complex loop structures. We develop a new testability measure, and utilize the RT-level structure of the data path, for cost-effective re-design of the circuit to make it easily testable, without having to either scan any flip-flop or breakloops directly. The non-scan DFT technique was applied to several data path circuits. Experimental results demonstrate the feasibility of producing non-scan testable data paths, which can be tested at-speed. The hardware overhead and the test application time required for the non-scan designs is significantly lower than the corresponding partial scan designs.