Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Computing binary decision diagrams for VHDL data types
EURO-DAC '94 Proceedings of the conference on European design automation
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Generation of BDDs from hardware algorithm descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Art of Software Testing
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SystemC
Automatic Generation of Validation Stimuli for Application-Specific Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Logic-level analysis of high-level faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Laerte++: an object oriented high-level TPG for systemC designs
Languages for system specification
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Redundant functional faults reduction by saboteurs synthesis [logic verification]
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
High-level test generation for hardware testing and software validation
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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This paper presents an analysis of the behavioral descriptions of embedded systems to generate behavioral test patterns used to perform the exploration of design alternatives based on testability. In this way, during the hardware/software partitioning of the embedded system, testability aspects can be considered. The paper presents an innovative error model for algorithmic (behavioral) descriptions, which allows for the generation of behavioral test patterns. They are converted into gate-level test sequences by using more or less accurate procedures based on scheduling information or both scheduling and allocation information. The paper experimentally shows that such converted gate-level test sequences provide a very high stuck-at fault coverage, when applied to different gate-level implementations of the given behavioral specification. For this reason, our behavioral test patterns can be used to explore testability alternatives, by simply performing fault simulation at the gate level with the same set of patterns without regenerating them for each circuit. Furthermore, whenever gate-level ATPGs are applied on the synthesized gate-level circuits, they obtain lower fault coverage, with respect to our behavioral test patterns, in particular when considering circuits with hard to detect faults.