Structured logic design with VHDL
Structured logic design with VHDL
Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Implicit Functionality and Multiple Branch Coverage (IFMB): a Testability Metric for RT-Level
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Redundant functional faults reduction by saboteurs synthesis [logic verification]
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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This paper proposes new fault models for VHDL behavioral descriptions of combinational logic circuits. The models are developed via abstraction of industry standard single-stuck-line (SSL) faults into the behavioral domain. A functional analysis technique is used to evaluate the effects of SSL faults on gate level implementations. Generalized functional faults are then abstracted into the behavioral domain by examining their relationship with the higher level language construct. Test vectors derived from the new behavioral fault models are applied to synthesized gate level realizations of an example arithmetic logic unit. Resulting gate level fault coverage is determined and used as a measure of effectiveness for the new fault models. Because the behavioral faults are derived from a functional analysis of low level faults, they provide improved fault coverage over previous fault models.