Chip-level modeling with VHDL
A heuristic chip-level test generation algorithm
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
A Behavioral Fault Simulator for Ideal
IEEE Design & Test
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models
Integration, the VLSI Journal
A goal tree based high-level test planning system for DSP real number models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
Behavioral Fault Modeling in a VHDL Synthesis Environment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Implicit Functionality and Multiple Branch Coverage (IFMB): a Testability Metric for RT-Level
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation
Journal of Electronic Testing: Theory and Applications
Redundant functional faults reduction by saboteurs synthesis [logic verification]
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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This paper presents two tools which facilitate the fault simulation of behavioral models described using VHDL. The first tool is the Behavioral Fault Mapper (BFM). The BFM algorithm accepts a fault-free VHDL model and a fault list of N faults from which it produces N faulty models. The process of mapping the faults in the fault list onto copies of the original VHDL model is automated. The N faulty models are immediately suitable for fault simulation. The second tool presented is the Test Bench Generator (TBG). The TBG algorithm creates the VHDL TestBench and all other files necessary to complete a batch-mode fault simulation of the N faulty models.