Logic testing and design for testability
Logic testing and design for testability
Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
VHDL, Hardware Description and Design
VHDL, Hardware Description and Design
Unified Methods for VLSI Simulation and Test Generation
Unified Methods for VLSI Simulation and Test Generation
Behavioral-Level Fault Simulation
IEEE Design & Test
IEEE Design & Test
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation
Journal of Electronic Testing: Theory and Applications
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A method of performing fault simulation at the behavioral level by propagating faults through behavioral hardware descriptions is presented. The method is accurate because it uses fault models only at the gate level. Since it does not duplicate computations at the behavioral level for each fault, it is, on the average, faster than existing methods. Examples in the Ideal hardware description language are used to discuss the basis for a fast behavioral fault simulator.