Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
VHDL modelling and analysis of fault secure systems
Proceedings of the conference on Design, automation and test in Europe
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A TSC evaluation function for combinational circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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This paper introduces a methodology for assessing the fault security attributes of Fault Secure (FS) circuits. Structural VHDL circuit descriptions are used to simulate the fault effects of reafistic transistor level defects that occur in CMOS ICs. Defective standard cells are simulated at the analog level of abstraction and the resultant fault effects are implemented in defect-injectable VHDL models to allow logic simulation. Typical fault effects include functional changes, propagation delay increases, sequential logic faults, stuck-at faults, reduced noise margins, and increased IDDQ. The defect-injectable VHDL models are swapped into FS circuit designs and the effects of the defects are analyzed in the context of the digital circuit. The FS circuits can then be assigned a figure of merit based on the ratio of detected defects to those that actually cause output errors. To facilitate the execution of the methodology, an integrated software tool has been developed that, in combination with a commercial VHDL simulation tool, provides an automated means for determining the figure of merit. Implemented using a GUI, the new tool is user friendly and flexible enough to be used with various logic circuits and different IC technologies. Three different checker, as benchmarks, wére evaluated to demonstrate the FSA tool and the methodology to assess their relative fault security.