Priority directed test generation for functional verification using neural networks

Authors:
Hao Shen;Yuzhuo Fu
Affiliations:
Shanghai Jiao Tong University, Shanghai, P.R. China;Shanghai Jiao Tong University, Shanghai, P.R. China
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 7
Cited 0

Hole analysis for functional coverage data

Proceedings of the 39th annual Design Automation Conference
A comparison of three verification techniques: directed testing, pseudo-random testing and property checking

Proceedings of the 39th annual Design Automation Conference
Neural Networks: A Comprehensive Foundation

Neural Networks: A Comprehensive Foundation
Database System Concepts

Database System Concepts
AMLETO: a multi-language environment for functional test generation

Proceedings of the IEEE International Test Conference 2001
Coverage directed test generation for functional verification using bayesian networks

Proceedings of the 40th annual Design Automation Conference
Industrial experience with test generation languages for processor verification

Proceedings of the 41st annual Design Automation Conference

Quantified Score

Hi-index	0.02

Visualization

Abstract

Functional verification is the bottleneck in delivering today's highly integrated electronic systems and chips. We should notice the simulation times and computation resource challenge in the automatic pseudo-random test generation and a novel solution named Priority Directed test Generation (PDG) is proposed in this paper. With PDG, a test vector which hasn't been simulated is granted a priority attribute. The priority indicates the possibility of detecting new bugs by simulating this vector. We show how to apply Artificial Neural Networks (ANNs) learning algorithm to the PDG problem. Several experiments are given to exhibit how to achieve better result in this PDG method.