An RT-level fault model with high gate level correlation
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Native Mode Functional Self-Test Generation for Systems-on-Chip
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
A software test program generator for verifying system-on-chips
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Proceedings of the 20th annual conference on Integrated circuits and systems design
Test Generation for Microprocessors
IEEE Transactions on Computers
Automatic detection of software defects: an industrial experience
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
Journal of Electronic Testing: Theory and Applications
Feedback-based coverage directed test generation: an industrial evaluation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Coverage-Directed Test Generation Automated by Machine Learning -- A Review
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in the system are identified and then dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. The results obtained by the evolutionary tool outperform those obtained by a skilled engineer on the same benchmark.