Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Formal Methods in System Design
Verification of Basic Block Schedules Using RTL Transformations
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Using highly optimized, custom circuits and fast dynamic array control structures, a small team of designers at the IBM Austin Research Laboratory has developed a one gigahertz microprocessor. This paper describes the custom datapath circuit technology ...