Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
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The well known Force Directed List Scheduling (FDLS) Algorithm uses a rigorous priority function called the Force of an operation. The force of an operation is governed by two components, namely the self-force of an operation and its successors' forces. The successor force in turn is governed by the self-force of all the descendants of the operation. FDLS is computationally intensive in its force calculations. For data flow dominated designs, a major portion of the FDLS execution time is spent in the computation of successor forces. However in this paper we observe that it is not always necessary to compute successor forces till the last successor level. We have shown in this paper that there usually exists a stabilization point after which successor force computations would not affect the quality of the schedule produced. This paper presents a concept of stability to show that it is possible to dynamically bound the successor force calculations in FDLS, up to a certain level of descendants. We have measured the performance of FDLS for a suite of high level synthesis benchmarks. Results presented in the paper show considerable reduction in execution time for the same schedule quality. This would allow a high-level synthesis tool to perform better design space exploration.