High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A compositional model for the functional verification of high-level synthesis results
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Introduction to High-Level Synthesis
IEEE Design & Test
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Hand-in-hand verification of high-level synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalence checking of scheduling with speculative code transformations in high-level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Translation validation of scheduling in high level synthesis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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We present a methodology for formal verification of scheduling phase of High-Level Synthesis (HLS) when speculative code motions are performed during this process. Verification relies on establishing functional equivalence between the result of scheduling and the behavioral specification of the design, using their FSMD models. We propose and formally define a relation between the two FSMDs that is less constrained than the strong equivalence, but stronger than weak equivalence. For verification of scheduling involving speculative code motions, we propose the notion of FSMD recomposition, a transformation that alters the state sequence and/or the operation of each state, while maintaining the functionality. The equivalence conditions are formulated in higher-order logic, and their correctness is verified in the theorem proving environment PVS. The entire verification flow, including formal model extraction and proof generation is fully automated.