High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An axiomatic basis for computer programming
Communications of the ACM
Formal Methods in System Design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Verification of Basic Block Schedules Using RTL Transformations
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalence checking of scheduling with speculative code transformations in high-level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path-based scheduling for synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
The growing design-productivity gap has made designers shift toward using high-level synthesis (HLS) techniques to generate register transfer level design from high-level languages. Unfortunately, this translation process is very complex and may introduce bugs into the generated design, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an equivalence checking method to validate the result of HLS scheduling against the initial high-level program. Finite state machine with data path (FSMD) models were used to represent designs before and after scheduling. The proposed method uses a bisimulation relation approach to prove equivalence. The automatically established bisimulation relation guarantees that for each execution sequence in the design before scheduling, a related and equivalent execution sequence exists in the design after scheduling and vice versa. Our method provides a unified way to deal with various scheduling optimizations. We have implemented our validation technique and compared it with a state-of-the-art HLS scheduling verification method. The promising results show the effectiveness and efficiency of our method.