High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A reordering technique for efficient code motion
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Introduction to Mathematical Theory of Computation
Introduction to Mathematical Theory of Computation
Formal Methods in System Design
Introduction to Algorithms
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
An approach to high-level synthesis system validation using formally verified transformations
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Compilers: Principles, Techniques, & Tools with Gradiance
Compilers: Principles, Techniques, & Tools with Gradiance
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Translation validation of scheduling in high level synthesis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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This paper presents a formal method for equivalence checking between the descriptions before and after scheduling in high-level synthesis (HLS). Both descriptions are represented by finite state machine with datapaths (FSMDs) and are then characterized through finite sets of paths. The main target of our proposed method is to verify scheduling employing code transformations -- such as speculation and common subexpression extraction (CSE), across basic block (BB) boundaries - which have not been properly addressed in the past. Nevertheless, our method can verify typical BB-based and path-based scheduling as well. The experimental results demonstrate that the proposed method can indeed outperform an existing state-of-the-art equivalence checking algorithm.