REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A scheduling and resource allocation algorithm for hierarchical signal flow graphs
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A technology-adaptive allocation of functional units and connections
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Bridge: a versatile behavioral synthesis system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
An integrated approach to retargetable code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient global register allocation for minimizing energy consumption
ACM SIGPLAN Notices
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Scalable interprocedural register allocation for high level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We developed a new algorithm for efficient register allocation and binding used in data path synthesis. Our algorithm determines both the number of registers and the mapping from variables to registers simultaneously during data path allocation so that the cost, i.e., area, of the registers and connections to/from the registers can be minimized. The algorithm selects the “best” register for each input and/or output variable of operations. This register allocation/binding algorithm is used with a data path allocation algorithm that exploits trade-off among all kinds of hardware elements. We present experimental results of our algorithm.