Computer networks
Microcontrollers: architecture, implementation, and programming
Microcontrollers: architecture, implementation, and programming
A global, dynamic register allocation and binding for a data path synthesis system
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data-path synthesis using path analysis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ISIS: a system for performance driven resource sharing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Functional synthesis using area and delay optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Clock period optimization during resource sharing and assignment
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Hardware synthesis and analysis of control-intensive designs from high level specifications
Hardware synthesis and analysis of control-intensive designs from high level specifications
How datapath allocation affects controller delay
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
False loops through resource sharing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Fast true delay estimation during high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus on control-flow intensive descriptions, characterized by the presence of mutually exclusive paths due to the presence of nested conditional branches and loops.We show that clustering multiple operations in the same state of the schedule, possibly leading to chaining of functional units (FUs) in the RTL circuit, is an effective way to minimize the total number of clock cycles, and hence total execution time. We present an assignment algorithm that is particularly effective for such design styles by minimizing data chaining and hence the clock period of the circuit, thereby leading to further reduction in total execution time.Existing resource sharing and assignment approaches for reducing the clock period of the resulting circuit either increase the resource allocation or use faster modules, both leading to leading to larger area requirements. In this paper we show that even when the type of available resource units and the number of resource units of each type is fixed, different assignments may lead to circuits with significant differences in clock period.We provide a comprehensive analysis of how resource sharing and assignment introduces long paths in the circuit. Based on the analysis, we develop an assignment algorithm that uses a high-level delay estimator to asign operations to a fixed set of available resources so as to minimize the clock period of the resultant circuit, with no or minimal effect on the area of the circuit. Experimental results on several conditional-intensive designs demonstrate the effectiveness of the assignment algorithm.