REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Introduction to algorithms
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A global, dynamic register allocation and binding for a data path synthesis system
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The ADAM advanced design automation system: overview, planner and natural language interface
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Algorithm 457: finding all cliques of an undirected graph
Communications of the ACM
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Computer
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
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In this work, we address the problem of register optimization that arises during high-level synthesis from hierarchical behavioral specifications containing a hierarchy of modules such as procedures, functions etc. Register optimization (or register sharing) is the process of grouping carriers in the specification such that each group can be safely assigned to a hardware register. Global register optimization by in-line expansion involves flattening the module hierarchy and using a heuristic register optimization procedure on the flattened description. Although in-line expansion leads to near-optimal number of registers, it is time consuming due to the large number of carrier compatibility relationships that must be considered. We present an efficient register optimization algorithm which achieves nearly the same effect of in-line expansion without actually in-line expanding at the specification level. It differs from other techniques as it employs a hierarchical optimization phase which exploits the properties of the module call graph and the information gathered during local carrier life-cycle analysis of each module. Experimental results on a number of examples show that the proposed algorithm produces nearly the same number of registers as in-line expansion based global optimization and is faster by a factor ranging from 1.5 to 18.3.