Design-flow and synthesis for ASICs: a case study
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Formal synthesis of circuits with a simple handshake protocol
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
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