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A computational approach for corner and vertex detection
International Journal of Computer Vision
A new kind of science
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems
The Journal of Supercomputing
Marching-pixels: a new organic computing paradigm for smart sensor processor arrays
Proceedings of the 2nd conference on Computing frontiers
Marching Pixels - Using Organic Computing Principles in Embedded Parallel Hardware
PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
High-speed smart camera with high resolution
EURASIP Journal on Embedded Systems
Realising emergent image preprocessing tasks in cellular-automaton-alike massively parallel hardware
International Journal of Parallel, Emergent and Distributed Systems - Emergent Computation
Distributed vision with smart pixels
Proceedings of the twenty-fifth annual symposium on Computational geometry
Orthogonal variant moments features in image analysis
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Concurrency and Computation: Practice & Experience
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In this paper, we present a class of emergent algorithms called Marching Pixels and a corresponding programmable parallel chip architecture. Marching Pixels can be used for real-time image processing in smart camera chips. They are based on hardware agents, which are virtually crawling in a pixel grid image to find attributes like centroid, rotation, and size of an arbitrary number of objects given in an image. Because of the distributed and local processing scheme of Marching Pixels, reply times in milliseconds can be fulfilled. This means that time is determined where pre-known objects are located and how they are oriented to the main axes of the image. We present an example Marching Pixels algorithm and corresponding application-specific and programmable parallel architectures. The latter contains a specific instruction set that allows not only the execution of Marching Pixels algorithms but also of arbitrary Cellular Automata algorithms as an embedded parallel processor. The strengths and weaknesses of this architecture concerning the realization as field-programmable gate arrays and application-specific integrated circuits are discussed by means of hardware synthesis results. These results are compared with the solution achievable on a real hardware like the Atom processor. Copyright © 2011 John Wiley & Sons, Ltd.