A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
The MPEG-4 Book
JPEG 2000: Image Compression Fundamentals, Standards and Practice
JPEG 2000: Image Compression Fundamentals, Standards and Practice
JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
Real-time sub-pixel cross bar position metrology
Real-Time Imaging
Smart Cameras as Embedded Systems
Computer
Goal-Directed Evaluation of Binarization Methods
IEEE Transactions on Pattern Analysis and Machine Intelligence
Implementation of a Wavelet Transform Architecture for Image Processing
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
Introduction to the Special Issue on Integrated Multimedia Platforms
IEEE Transactions on Circuits and Systems for Video Technology
A new time distributed DCT architecture for MPEG-4 hardware reference model
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Neural Networks
Smart camera based on embedded HW/SW coprocessor
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Concurrency and Computation: Practice & Experience
Scene-based non-uniformity correction: From algorithm to implementation on a smart camera
Journal of Systems Architecture: the EUROMICRO Journal
Efficient smart-camera accelerator: A configurable motion estimator dedicated to video codec
Journal of Systems Architecture: the EUROMICRO Journal
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High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded processing. Two types of algorithms have been implemented. A compression algorithm, specific to high-speed imaging constraints, has been implemented. This implementation allows to reduce the large data flow (6.55 Gbps) and to propose a transfer on a serial output link (USB 2.0). The second type of algorithm is dedicated to feature extraction such as edge detection, markers extraction, or image analysis, wavelet analysis, and object tracking. These image processing algorithms have been implemented into an FPGA embedded inside the camera. These implementations are low-cost in terms of hardware resources. This FPGA technology allows us to process in real time 500 images per second with a 1280 × 1024 resolution. This camera system is a reconfigurable platform, other image processing algorithms can be implemented.