Reconfigurable pipelined 2-D convolvers for fast digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Goal-Directed Evaluation of Binarization Methods
IEEE Transactions on Pattern Analysis and Machine Intelligence
FPGA Based Controller for Heterogeneous Image Processing System
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Proceedings of the 42nd annual Design Automation Conference
High-speed smart camera with high resolution
EURASIP Journal on Embedded Systems
A Computer Vision based Whiteboard Capture System
WACV '08 Proceedings of the 2008 IEEE Workshop on Applications of Computer Vision
Video compression with custom computers
IEEE Transactions on Consumer Electronics
Design of real-time image enhancement preprocessor for CMOS image sensor
IEEE Transactions on Consumer Electronics
Scene-based non-uniformity correction: From algorithm to implementation on a smart camera
Journal of Systems Architecture: the EUROMICRO Journal
Efficient smart-camera accelerator: A configurable motion estimator dedicated to video codec
Journal of Systems Architecture: the EUROMICRO Journal
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This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging technology because the coprocessor unit is integrated into the image acquisition loop. The acquisition and coprocessing architecture are compatible with the majority of CMOS sensors. It enables the dynamic selection of a wide variety of acquisition modes as well as the reconfiguration and implementation of high-performance image preprocessing algorithms (calibration, filtering, denoising, binarization, pattern recognition). Furthermore, the processing and data transfer, from the CMOS sensor to the processor, can be operated simultaneously to increase achievable performances. The coprocessor architecture has been designed so as to obtain a unit that can be configured on the fly, in terms of type and number of chained processing stages (up to 8 successive predefined preprocessing stages), during the image acquisition process that can be defined by the user according to each specific application requirement. Examples of acquisition and processing performances are reported and compared to classical image acquisition systems based on standard modular PC platforms. The experimental results show a considerable increase of the achievable performances.