IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
High-speed smart camera with high resolution
EURASIP Journal on Embedded Systems
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
Journal of Signal Processing Systems
Smart camera based on embedded HW/SW coprocessor
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Journal of Signal Processing Systems
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A block-based gradient descent search algorithm for block motion estimation in video coding
IEEE Transactions on Circuits and Systems for Video Technology
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
IEEE Transactions on Circuits and Systems for Video Technology
Fast Motion Estimation Robust to Random Motions Based on a Distance Prediction
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the Scalable Video Coding Extension of the H.264/AVC Standard
IEEE Transactions on Circuits and Systems for Video Technology
ACIVS'12 Proceedings of the 14th international conference on Advanced Concepts for Intelligent Vision Systems
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Smart cameras are used in a large range of applications. Usually the smart cameras transmit the video or/and extracted information from the video scene, frequently on compressed format to fit with the application requirements. An efficient hardware accelerator that can be adapted and provide the required coding performances according to the events detected in the video, the available network bandwidth or user requirements, is therefore a key element for smart camera solutions. We propose in this paper to focus on a key part of the compression system: motion estimation. We have developed a flexible hardware implementation of the motion estimator based on FPGA component, fully compatible with H.264, which enables the integer motion search, the fractional search and variable block size to be selected and adjusted. The main contributions of this paper are the definition of an architecture allowing flexibility and some new hardware optimizations of the architecture of the motion estimation allowing the improvement of the performances (computing time or hardware resources) compared to the state of the art. The paper describes the design and proposes a comparison with state-of-art architectures. The obtained FPGA based architecture can process integer motion estimation on 720x576 video streams at 67fps using full search strategy, and sub-pel refinement up to 650KMacroblocks/s.