Hardware implementation of a configurable motion estimator for adjusting the video coding performances

  • Authors:

  • Wajdi Elhamzi;Julien Dubois;Johel Miteran;Mohamed Atri;Rached Tourki

  • Affiliations:

  • Laboratory Le2i, UMR CNRS 6306, University of Burgundy, Dijon, France;Laboratory Le2i, UMR CNRS 6306, University of Burgundy, Dijon, France;Laboratory Le2i, UMR CNRS 6306, University of Burgundy, Dijon, France;Laboratory of E$#956/E, Faculty of Sciences of Monastir, University of Monastir, Tunisia;Laboratory of E$#956/E, Faculty of Sciences of Monastir, University of Monastir, Tunisia

  • Venue:
  • ACIVS'12 Proceedings of the 14th international conference on Advanced Concepts for Intelligent Vision Systems
  • Year:
  • 2012

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Abstract

Despite the diversity of video compression standard, the motion estimation still remains a key process which is used in most of them. Moreover, the required coding performances (bit-rate, PSNR, image spatial resolution, etc.) depend obviously of the application, the environment and the network communication. The motion estimation can therefore be adapted to fit with these performances. Meanwhile, the real time encoding is required in many applications. In order to reach this goal, we propose in this paper a hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search and variable block size to be selected and adjusted. Hence this novel architecture, especially designed for FPGA targets, proposes high-speed processing for a configuration which supports the variable size blocks and quaterpel refinement, as described in H.264.