A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization

  • Authors:

  • Yang Song;Zhenyu Liu;Takeshi Ikenaga;Satoshi Goto

  • Affiliations:

  • The authors are with Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 808-0135 Japan. E-mail: syang@asagi.waseda.jp,;The author is with Kitakyushu Foundation for the Advancement of Industry Science and Technology, Kitakyushu-shi, 808-0135 Japan.;The authors are with Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 808-0135 Japan. E-mail: syang@asagi.waseda.jp,;The authors are with Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 808-0135 Japan. E-mail: syang@asagi.waseda.jp,

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2006

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Abstract

A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 μm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25°C), a clock frequency of 266 MHz can be achieved.