High-level algorithmic complexity evaluation for system design
Journal of Systems Architecture: the EUROMICRO Journal
Smart camera based on embedded HW/SW coprocessor
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
An efficient demosaiced image enhancement method for a low cost single-chip CMOS image sensor
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
| Hi-index | 0.43 |
This paper presents a design of the real-time digital image enhancement preprocessor for a CMOS image sensor. The CMOS image sensor offers various advantages while it provides lower-quality images than the CCD does. In order to compensate for the physical limitation of the CMOS sensor, a spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19 K logic gates, which is suitable for a low-cost one-chip PC camera. The test system was implemented on a FPGA chip in real-time mode, and performed successfully