Image Sensors and Signal Processing for Digital Still Cameras
Image Sensors and Signal Processing for Digital Still Cameras
High-speed smart camera with high resolution
EURASIP Journal on Embedded Systems
Smart camera based on embedded HW/SW coprocessor
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
A noise reduction filter for full-frame data imaging devices
IEEE Transactions on Consumer Electronics
| Hi-index | 0.00 |
Raw output data from image sensors tends to exhibit a form of bias due to slight on-die variations between photodetectors, as well as between amplifiers. The resulting bias, called fixed pattern noise (FPN), is often corrected by subtracting its value, estimated through calibration, from the sensor's raw signal. This paper introduces an on-line scene-based technique for an improved fixed-pattern noise compensation which does not rely on calibration, and hence is more robust to the dynamic changes in the FPN which may occur slowly over time. This article first gives a quick summary of existing FPN correction methods and explains how our approach relates to them. Three different pipeline architectures for realtime implementation on a FPGA-based smart camera are then discussed. For each of them, FPGA implementations details, performance and hardware costs are provided. Experimental results on a set of seven different scenes are also depicted showing that the proposed correction chain induces little additional resource use while guarantying high quality images on a wide variety of scenes.