A practical evaluation of the performance of the Impulse CoDeveloper HLS tool for implementing large-kernel 2-D filters

  • Authors:
  • Carlos Colodro-Conde;F. Javier Toledo-Moreo;Rafael Toledo-Moreo;J. Javier Martínez-Álvarez;Javier Garrigós-Guerrero;J. Manuel Ferrández-Vicente

  • Affiliations:
  • Dpto. Electrónica, Tecnología de Computadoras y Proyectos, Universidad Politécnica de Cartagena, Cartagena, Spain;Dpto. Electrónica, Tecnología de Computadoras y Proyectos, Universidad Politécnica de Cartagena, Cartagena, Spain;Dpto. Electrónica, Tecnología de Computadoras y Proyectos, Universidad Politécnica de Cartagena, Cartagena, Spain;Dpto. Electrónica, Tecnología de Computadoras y Proyectos, Universidad Politécnica de Cartagena, Cartagena, Spain;Dpto. Electrónica, Tecnología de Computadoras y Proyectos, Universidad Politécnica de Cartagena, Cartagena, Spain;Dpto. Electrónica, Tecnología de Computadoras y Proyectos, Universidad Politécnica de Cartagena, Cartagena, Spain

  • Venue:
  • Journal of Real-Time Image Processing
  • Year:
  • 2014

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Abstract

Bidimensional convolution is a low-level processing algorithm which is of great interest in many areas, but its high computational cost limits the size of the kernels, especially in real-time embedded systems. This work describes the process of designing 2-D filters with large kernels (up to 50 脳 50 coefficients) using the Impulse CoDeveloperTM high-level synthesis (HLS) tool. The purpose of this paper is twofold: first, to provide a practical guide for designers willing to make the most of an HLS tool like Impulse CoDeveloper, and second, to compare the results, in terms of area utilization, minimum clock period and power consumption, with implementations developed using lower-level design tools. The results show that RTL-based implementations can achieve higher throughputs (up to 44 % faster) than CoDeveloper-based ones. Nevertheless, CoDeveloper can also meet the high-performance requirements of the most demanding real-time applications, but with less effort and shorter design cycles.